Switched Memory Architectures |
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| Inventors: Dr. Sanjay Rajopadhye, Mr. Gautam Gupta, Mr. Lakshminarayanan Renganarayana Summary of the Technology: Switch Memory Architectures (SMAs) are a class of parallel architectures intended for a direct silicon implementation. They are tailored for the high performance implementation of the compute-intensive kernels of applications. They are a strict generalization of systolic architectures—a well accepted design for high performance implementation1. Systolic Architectures are an n-dimensional, locally connected grid of simple processing elements (PEs). Each PE is pre-configured for a specific task and thus has no instruction overhead. Precise data-transfer and control between the PEs result in the parallel solution of the application. SMAs relax the “locality-constraint” on the PEs of systolic architectures. They are a grid of PEs connected through the ISWITCH which allows long connections that can be rapidly, easily and dynamically reconfigured. The reconfiguration, however, is restricted in scope, and thus has a low cost. Nevertheless, they are necessary and sufficient for an efficient (optimal under certain constraints) regular implementation of the targeted applications. The above claim is a consequence of a well developed formal model (called the polyhedral model) that permits the expression of these algorithms. Systematic derivation of systolic architectures is possible within the polyhedral model. However, the locality constraint explained earlier has limited their efficiency. Relaxation of this constraint, inspired by advancements in silicon fabrication, leads to SMAs. Thus, SMAs inherit the research on formal theory, and the compilation framework for the systematic derivation of architectures for these applications. Patent: Licensing Contact: |
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This page was last updated October 1, 2006. |